IonQ

◐ Design-level API

This page documents qalgora-Q API design, architecture, or adaptation workflows. Code examples illustrate intended usage and are not guaranteed to run in the current reference implementation.

IonQ builds trapped-ion processors with all-to-all qubit connectivity, accessed directly or through Braket and Azure. It reports performance in vendor-defined algorithmic qubits (#AQ).

Systems

The #AQ figures and gate fidelities below are vendor-reported ("厂商宣称 / reported"); as of the documentation review date, public sources read this way, and specifics defer to IonQ's official announcements.

System	Performance (reported)	Notes
Aria	#AQ25 (reported)	Earlier commercial system (~99.4% 2-qubit, reported)
Forte / Forte Enterprise	#AQ36 (reported)	Commercial flagship, all-to-all (~99.6% 2-qubit, reported); Enterprise is data-center-ready
Tempo	#AQ64 (reported)	~100 physical qubits; IonQ reports #AQ64 on a development system Oct 2025, with systems shipping to customers in 2026

IonQ reports a 99.99% two-qubit gate fidelity ("four nines") result on R&D prototypes (Oct 2025), which it positions as a foundation for its planned 256-qubit-class 2026 systems. Treat this as a vendor claim pending independent confirmation.

Native gates & connectivity

Aspect	IonQ hardware
Native 1-qubit	GPI, GPI2 (single-qubit rotations on the Bloch equator)
Native 2-qubit	MS (Mølmer–Sørensen) / ZZ entangling gate
Connectivity	All-to-all — every ion can entangle with every other

Access routes

Route	Target
Direct IonQ cloud	`set_target("ionq", machine="forte")`
Amazon Braket	`arn:aws:braket:us-east-1::device/qpu/ionq/Forte-1`
Azure Quantum	`machine="ionq.qpu.forte-1"`

Submission is a planned adapter workflow

Submitting to IonQ (directly or via Braket / Azure) is a planned adapter workflow, not a native qalgora-Q capability. The open reference build runs locally; the remote set_target and submission lines below are commented as a planned flow. (bell is a predefined kernel from earlier in these docs.)

import qalgora
# Planned IonQ adapter — NOT in the open reference build.
# export QALGORA_IONQ_API_KEY for the direct cloud, then:
# qalgora.set_target("ionq", machine="forte")          # remote submission — planned
# counts = qalgora.sample(bell, shots_count=1000)       # bell = predefined kernel

Reference build runs locally — not real hardware

This example targets a remote cloud/QPU, but the open reference build does not submit to a real machine — it warns and falls back to the local CPU statevector simulator, returning simulated results. Submitting to an actual device (e.g. 天衍/TianYan, IBM, IonQ, Origin) requires the vendor’s own SDK and credentials.

Error mitigation

IonQ offers debiasing and symmetrization to average out coherent errors. qalgora-Q exposes the same idea via resilience levels on observe.

Why all-to-all?

Any qubit can interact with any other — no SWAP networks, so shallower circuits.
High two-qubit fidelity makes deep variational and chemistry circuits practical.
The #AQ metric captures usable scale better than a raw physical-qubit count.

Roadmap (vendor roadmap, not realized capability)

IonQ announced and completed its acquisition of Oxford Ionics in 2025, bringing chip-scale, semiconductor-fabricated ion traps and 2D arrays. IonQ's published roadmap: 256+ qubits / 12 logical (2026) → 10,000 qubits / 800 logical (2027) → 20,000 qubits with photonic interconnects (2028) → ~2,000,000 physical / ~80,000 logical (2030), all at a stated 99.99% gate fidelity. These are vendor roadmap targets, not realized capability; as of the documentation review date, specifics defer to IonQ's official announcements.

Quantum networking

IonQ is also building the IonQ Quantum Network — including space-based QKD — via acquisitions (Lightsynq repeaters, ID Quantique, Capella, Qubitekk, Skyloom), targeting clustered, networked quantum computing by 2028.

References

IonQ, Forte system specifications. ionq.com

IonQ

◐ 设计接口

本页描述的是 qalgora-Q 的接口设计、架构设计或适配工作流。相关代码用于说明预期用法，当前参考实现不保证可以直接运行。

IonQ 研制具备全连接量子比特的离子阱处理器，可直连访问或通过 Braket 与 Azure 接入，并以厂商定义的算法量子比特（#AQ）衡量性能。

系统

下表中的 #AQ 数值与门保真度均为厂商宣称（reported）；截至文档核对日期，公开资料如此，具体以 IonQ 官方公告为准。

系统	性能（厂商宣称）	备注
Aria	#AQ25（厂商宣称）	早期商用系统（双比特约 99.4%，厂商宣称）
Forte / Forte Enterprise	#AQ36（厂商宣称）	商用旗舰，全连接（双比特约 99.6%，厂商宣称）；Enterprise 面向数据中心
Tempo	#AQ64（厂商宣称）	约 100 个物理量子比特；IonQ 称 #AQ64 于 2025 年 10 月在开发系统上达成，系统于 2026 年向客户交付

IonQ 宣称在 R&D 原型上取得 99.99% 双比特门保真度（“四个九”）结果（2025 年 10 月），并将其定位为其规划中 2026 年 256 比特级系统的基础。在独立确认前，应将其视为厂商宣称。

原生门与连通性

特性	IonQ 硬件
原生单量子比特门	GPI、GPI2（Bloch 赤道上的单量子比特旋转）
原生双量子比特门	MS（Mølmer–Sørensen）/ ZZ 纠缠门
连通性	全连接——每个离子均可与其他任意离子纠缠

接入方式

方式	目标
直连 IonQ 云	`set_target("ionq", machine="forte")`
Amazon Braket	`arn:aws:braket:us-east-1::device/qpu/ionq/Forte-1`
Azure Quantum	`machine="ionq.qpu.forte-1"`

import qalgora
# 规划中的 IonQ 适配器 —— 开放参考实现中不包含。
# 先为直连云导出 QALGORA_IONQ_API_KEY，再执行：
# qalgora.set_target("ionq", machine="forte")          # 远程提交——规划中
# counts = qalgora.sample(bell, shots_count=1000)       # bell 为预定义内核

参考实现仅本地运行 · 非真机

此示例虽指向远程云端/QPU，但开放参考实现不会真正提交到真机 —— 它会给出告警并回退到本地 CPU 态矢量模拟器，返回模拟结果，不会真正提交到天衍等真机。真正提交真机需使用对应厂商的 SDK 与凭证。

纠错缓解

IonQ 提供去偏与对称化技术，用于平滑相干误差。qalgora-Q 通过韧性等级在 observe 上暴露相同机制。

为何选择全连接

任意量子比特之间均可直接交互，无需 SWAP 网络，线路深度更浅。
高双比特保真度使深层变分与化学线路切实可行。
#AQ 指标比原始物理量子比特数更能反映实际可用规模。

路线图（厂商路线图，非已实现能力）

IonQ 于 2025 年宣布并完成对 Oxford Ionics 的收购，引入芯片级、半导体工艺制造的离子阱与二维阵列。IonQ 公布的路线图为：256+ 比特 / 12 逻辑（2026） → 10,000 比特 / 800 逻辑（2027） → 20,000 比特并引入光子互连（2028） → 约 200 万物理 / 约 8 万逻辑（2030），门保真度均称为 99.99%。以上为厂商路线图目标，而非已实现能力；截至文档核对日期，具体以 IonQ 官方公告为准。

量子网络

IonQ 还通过一系列收购（Lightsynq 中继器、ID Quantique、Capella、Qubitekk、Skyloom）构建 IonQ Quantum Network（含天基 QKD），目标在 2028 年实现集群化、网络化的量子计算。

参考文献

IonQ, Forte system specifications. ionq.com

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