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Performance: Gate Fusion

○ Planned · Not yet implemented
The capabilities described on this page are planned and not yet implemented or released. They explain future design directions and should not be interpreted as delivered features.

Gate fusion is a planned high-performance backend optimization: it would merge adjacent gates into a single larger matrix before simulation, cutting the number of state updates on large circuits. It is not part of the open CPU reference build today.

Enabling fusion (planned)

Planned backend — not in the open reference build yet
This is a planned high-performance/GPU optimization that the open CPU reference build does not include today. The code is shown for the intended interface and is commented out so the snippet stays runnable.
import qalgora
# Planned high-performance backend — not in the open reference build yet:
# qalgora.set_target("gpu", option="fp32")
# fuse up to 4-qubit blocks before applying to the statevector
# qalgora.set_simulation_option("gate_fusion", level=4)
# counts = qalgora.sample(deep_kernel, shots_count=1000)
Specification API — not in the open reference build yet
This example shows a qalgora-Q specification API (or a third-party library) that the open reference build does not bundle today. It documents the intended interface; to run code now, use the reference build’s supported core API.

When it helps

  • Deep circuits — many single-qubit rotations collapse into fewer matrix ops.
  • Statevector targets — could in theory reduce repeated passes over the 2ᴺ amplitudes.
  • Large qubit counts — memory bandwidth, not gate count, dominates runtime.
Trade-off
Higher fusion levels build bigger intermediate matrices. A 3–4 qubit fusion block is a common empirical compromise, but the best level must be determined by benchmarking your circuit and hardware.

性能优化：门融合

○ 规划中
本页所述能力属于规划功能，当前尚未发布或尚未实现。相关内容仅用于说明未来设计方向，不应理解为已交付能力。

门融合是一项规划中的高性能后端优化：它会在模拟前将相邻的门合并为一个更大的矩阵，从而减少大规模线路的态矢量更新次数。开放的 CPU 参考实现目前尚未包含此功能。

启用门融合（规划中）

规划中 · 尚未发布
这是一项规划中的高性能/GPU 优化，开放的 CPU 参考实现目前尚未包含。此处代码仅用于说明预期接口，并已注释以保证片段可运行。
import qalgora
# 规划中的高性能后端，开放参考实现暂未包含：
# qalgora.set_target("gpu", option="fp32")
# 在作用于态矢量前，融合至多 4 比特的门块
# qalgora.set_simulation_option("gate_fusion", level=4)
# counts = qalgora.sample(deep_kernel, shots_count=1000)
规范接口 · 参考实现暂未包含
此示例展示的是 qalgora-Q 规范中的接口（或第三方库），开放参考实现目前尚未内置，仅用于说明预期用法；如需立即运行，请使用参考实现已支持的核心 API。

适用场景

  • 深层线路——大量单量子比特旋转可合并为更少的矩阵运算。
  • 态矢量目标——理论上可减少对 2ᴺ 个振幅的重复遍历。
  • 大量子比特数——运行时瓶颈在内存带宽而非门数量。
权衡
融合级别越高，中间矩阵越大。3–4 比特融合块是常见经验折中，但最佳级别需基准测试确定。