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Extending qalgora-Q

○ Planned · Not yet implemented
The capabilities described on this page are planned and not yet implemented or released. They explain future design directions and should not be interpreted as delivered features.

Add your own simulator or hardware backend behind the same kernel API.

Planned — not runnable (规划中·暂不可运行)
The C++ compiler/library has not been released, so the code on this page cannot be compiled or run. The base classes, registration macros, configs, and build commands shown across the different sections are separate design drafts — treat the published release as authoritative for the exact signatures.

Anatomy of a target

A target is a small configuration that tells the compiler how to lower qalgora IR and where to send the resulting program. Register one with a .yml config plus a runtime plugin.

# my_backend/target.yml (excerpt)
# name: my-sim
# description: "Custom statevector simulator"
# library-mode: true
# platform-library: qalgora-em-default

Implementing a circuit simulator

#include "qalgora/qis/execution_manager.h"

class MySimulator : public qalgora::CircuitSimulator {
public:
  void apply(const std::string &gate,
             const std::vector<std::size_t> &qubits,
             const std::vector<double> &params) override {
    // update your state representation here
  }
  std::vector<std::size_t> sample(const std::vector<std::size_t> &qubits,
                                  int shots) override {
    // return measured bitstrings
  }
};

QALGORA_REGISTER_SIMULATOR(MySimulator, "my-sim")
C++ API is planned — won’t run today
The runnable reference build is Python-only; the C++ library, its headers and the build tooling shown here are a planned interface and are not published yet, so this snippet will not compile or run as-is. Use the Python API against the reference build to actually run these examples today.

Using your backend

qalgora.set_target("my-sim")
print(qalgora.sample(my_kernel))
Hardware backends
Targeting a real QPU usually also involves authentication, job lifecycle management, shots/measurement formats, native gate sets and topology, parameter binding, and result schemas; ServerHelper is one of the planned adaptation entry points.

扩展 qalgora-Q

○ 规划中
本页所述能力属于规划功能，当前尚未发布或尚未实现。相关内容仅用于说明未来设计方向，不应理解为已交付能力。

在同一内核 API 背后接入自定义模拟器或硬件后端。

规划中·暂不可运行
C++ 编译器/库尚未发布，本页代码不可编译运行；不同小节展示的基类、注册宏、配置与构建命令为不同设计草案，具体签名以发布版为准。

一个目标后端由什么构成

目标后端就是一小段配置，告诉编译器怎样把 qalgora IR 逐级下译，以及把生成的程序发到哪里。写一个 .yml 配置文件，再配上运行时插件，就能完成注册。

# my_backend/target.yml (excerpt)
# name: my-sim
# description: "Custom statevector simulator"
# library-mode: true
# platform-library: qalgora-em-default

实现电路模拟器

#include "qalgora/qis/execution_manager.h"

class MySimulator : public qalgora::CircuitSimulator {
public:
  void apply(const std::string &gate,
             const std::vector<std::size_t> &qubits,
             const std::vector<double> &params) override {
    // update your state representation here
  }
  std::vector<std::size_t> sample(const std::vector<std::size_t> &qubits,
                                  int shots) override {
    // return measured bitstrings
  }
};

QALGORA_REGISTER_SIMULATOR(MySimulator, "my-sim")
C++ 接口为规划中 · 暂不可运行
可运行的参考实现仅提供 Python；此处展示的 C++ 库 头文件与构建工具属于规划中的接口 尚未发布 因此该片段当前无法直接编译或运行。若要真正运行这些示例 请使用 Python API 对接参考实现。

使用自定义后端

qalgora.set_target("my-sim")
print(qalgora.sample(my_kernel))
硬件后端
对接真实 QPU 通常还需处理认证、任务生命周期、shots/测量格式、原生门集与拓扑、参数绑定、结果 schema；ServerHelper 是规划中的适配入口之一。